The invention relates generally to semiconductor devices and integrated circuit fabrication and, in particular, to structures for a circuit including field-effect transistors and methods for fabricating and operating such circuits.
Complementary-metal-oxide-semiconductor (CMOS) processes may be used to build a combination of p-type and n-type field-effect transistors that are used to construct, for example, logic cells. Field-effect transistors generally include a body defining a channel region, a source, a drain, and a gate electrode. When a control voltage exceeding a characteristic threshold voltage is applied to the gate electrode, carrier flow occurs in the channel region between the source and drain to produce a device output current.
Special tap cells may be periodically inserted in a CMOS digital layout based on tap rules and may be used during operation to bias the back gates of the p-type and n-type field-effect transistors. A positive voltage may be supplied from each tap cell to the n-wells of the p-type field-effect transistors in a logic cell to bias their back gates. A negative voltage may be supplied from each tap cell to the p-wells of n-type field-effect transistors in the logic cell to bias their back gates. The back gate bias may be used to enhance transistor performance and to reduce leakage power consumption. However, a problem with conventional back gate biasing is that a negative voltage is often not available in a design or in a system. Another problem with conventional back gate biasing is the area and power required for a bias generator needed to generate the positive and negative voltages. Yet another problem with conventional back gate biasing is the need for a net of analog bias lines to route the positive and negative voltages on a chip according to high voltage rules.
Improved structures for a circuit including field-effect transistors and methods for fabricating and operating such circuits are needed.